This invention relates to integrated circuit device fabrication methods and, more particularly, to methods of forming self-aligned contact structures in semiconductor integrated circuit devices.
Attempts to increase device integration density in microelectronic integrated circuits have typically resulted in the fabrication of smaller and smaller devices that are spaced more closely together. In order to electrically access these devices, conventional techniques to photolithographically define the location of contact holes to these devices have also had to improve. Such improvements have typically included the development of photolithographic alignment techniques having reduced tolerances. Alternatively, attempts to reduce contact hole size may not represent an acceptable approach when forming highly integrated devices because reductions in contact hole size typically lead to substantial and unacceptable increases in contact resistance.
Techniques to reduce photolithographic alignment tolerances have typically not scaled at the same rate as techniques to scale the size of microelectronic devices. To address this limitation associated with photolithographic alignment, self-aligned contact hole fabrication techniques that are less dependent on photolithographic accuracy have been developed.
A method of forming self-aligned contact holes is taught in U.S. Pat. No. 5,897,372 to Howard entitled xe2x80x9cFormation of a self-aligned integrated circuit structure using silicon-rich nitride as a protective layerxe2x80x9d. According to the U.S. Pat. No. 5,897,372, a gate electrode surrounded by an upper protection layer and a side-wall spacer is formed on a semiconductor substrate. A thin silicon-rich silicon nitride layer and a thick inter-layer insulating layer are sequentially formed on the entire surface of the resultant structure. The inter-layer insulating layer and the silicon-rich silicon nitride layer are dry-etched in sequence to form a self-aligned contact hole exposing the substrate between the gate electrodes. Here, a width of the self-aligned contact hole is wider than a space between the gate electrodes in order to maximize the exposed area of the substrate. Accordingly, an edge portion of the protection layer on the gate electrode is exposed by the self-aligned contact hole. At this time, in the event both the protection layer and the spacer are formed of a silicon oxide layer, the gate electrode may be exposed due to the over etching during a dry-etching process for forming the self-aligned contact hole. Thus, in order to overcome the above problem, both the protection layer and the spacer should be formed of silicon nitride layer having etch selectivity with respect to the inter-layer insulating layer or the thickness of the silicon-rich silicon nitride layer should be increased. However, the silicon nitride layer and the silicon-rich silicon nitride layer have higher dielectric constants than the silicon oxide layer. Therefore, the parasitic capacitance between the interconnection filling the self-aligned contact hole and the gate electrode is increased and such increase may degrade the electrical characteristics of the integrated circuit.
As a result, such self-aligned contact hole fabrication techniques may still be prone to reliability problems when photolithographic alignment techniques having relatively large alignment tolerances are used. Thus, notwithstanding such self-alignment techniques, there continues to be a need for improved methods of forming contact holes in highly integrated circuit substrates.
It is therefore an object of the present invention to provide methods of forming self-aligned contact structure, which can minimize the parasitic capacitance between two adjacent conductive layers and improve the reliability of the alignment techniques.
It is another object of the present invention to provide methods of forming self-aligned contact structure, which can minimize the contact resistance.
These and other objects, advantages and features of the present invention may be provided by methods of forming self-aligned contact structure of integrated circuit devices (e.g., memory devices). These methods improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device patterns and thereby potentially expose the patterns in an adverse manner. According to one embodiment of the present invention, a method of forming self-aligned contact structure includes the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a surface of the substrate with a capping insulating layer. The capping insulating layer is then covered with an upper inter-layer insulating layer filling gap regions between the interconnection patterns. The upper inter-layer insulating layer and the capping insulating layer are then dry-etched in sequence to form a narrow contact hole, e.g., a first contact hole that exposes the substrate, but preferably does not expose the interconnection patterns. In this embodiment, the capping insulating layer may be formed of silicon nitride layer. The first contact hole is then widened in a self-aligned manner using the capping insulating layer as an etch-stop layer. In particular, the first contact hole is widened to form a second contact hole exposing the capping insulating layer on the sidewalls of the interconnection patterns, by wet etching sidewalls of the first contact hole using an etchant that etches the upper inter-layer insulating layer faster than the capping insulating layer. In this manner, the first contact hole may be formed to initially compensate for potential misalignment errors and then a self-aligned wet etching step may be performed to widen the first contact hole so that low resistance contacts (e.g., contact plugs) can be provided in the second contact hole. During this widening step, the selectivity of the wet etchant can be made high to reduce the likelihood that the interconnection patterns will become exposed to the second contact hole.
According to another aspect of the present invention, the step of forming the second contact hole is preferably followed by the steps of forming an oxide spacer on a sidewall of the second contact hole and then etching a protrusion of the capping insulating layer extending opposite the substrate, using the oxide spacer as an etching mask. This latter sequence of steps is preferably preformed in order to increase the area of the substrate that is exposed by the second contact hole and thereby lower the contact resistance between a subsequently formed contact plug and the substrate.
According to another embodiment of the present invention, a method of forming self-aligned contact structure of an integrated circuit memory device comprises the steps of forming a lower inter-layer insulating layer on a semiconductor substrate and then forming a pad contact hole in the lower inter-layer insulating layer. A pad plug is then formed in the pad contact hole using conventional techniques. First and second bit line patterns are then formed at adjacent locations on an upper surface of the lower inter-layer insulating layer. A capping insulating layer that covers the pad plug and the first and second bit line patterns is then deposited. An upper interlayer insulating layer is then formed on the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then etched in sequence to form a first contact hole that exposes a first portion of the underlying pad plug. The first contact hole is then widened in a preferred self-aligned manner by selectively etching the sidewalls of the first contact hole with an etchant that etches the upper interlayer insulating layer at a faster rate than the capping insulating layer, thereby forming a second contact hole exposing the capping insulating layer on the sidewalls of the bit line patterns. Next, an oxide spacer is formed on the sidewall of the second contact hole. After the oxide spacer has been formed, the capping insulating layer is again etched to expose a second portion of the pad plug that is greater than the first portion. This step is preferably performed using the oxide spacer as an etching mask. Alternatively, the oxide spacer may be formed with an etching process showing a poor etch selectivity respect to the capping insulating layer so that the capping insulating layer is etched concurrently with the formation of the oxide spacer. In this case, it is not required to additionally etch the capping insulating layer with an extra etching process. The second contact hole is then filled with a contact plug.